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Internal Dimming MOSFET
I peak =45μA
I inductor
A dimming MOSFET (400 V N-channel MOSFET; such
as FDD3N40) is incorporated in the FAN7340. The
power transistor is produced using Fairchild ’ s
m
T s
I ramp
m1
m2
proprietary, planar stripe, DMOS technology. This
advanced technology is tailored to minimize on-state
V SC
5k
V CS
R1
V S
resistance (R DS(on) =3.4 ? ), to provide superior switching
performance. This device is suited for high-efficiency
SMPS and shows desirable thermal characteristic during
operation. To prevent initial LED current overshoot at low
V CMP
R S
V ADIM levels, gate resistance of the internal dimming FET
is designed as 5 k ? ? experimentally.
Figure 27.
Slope Compensation Block Diagram
Feedback Loop Compensation
Stable closed-loop control can be accomplished by
connecting a compensation network between COMP and
GND. The compensation needed to stabilize the
converter can be either a Type-I circuit (a simple
integrator) or a Type-II circuit (and integrator with and
additional pole-zero pair). The type of the compensation
circuit required is dependent on the phase of the power
stage at the crossover frequency.
FAN7340 adopts a Type-II compensator circuit.
Cycle-by-Cycle Over-Current Protection
In boost topology, the switch can be damaged in
abnormal conditions (inductor short, diode short, output
short). It is always necessary to sense the switch current
to protect against over-current failures. Switch failures
due to excessive current can be prevented by limiting I d.
I d
DRV
Programmed Current Control
FAN7340 uses a Current-Mode control method. Current-
5k
CLK+LEB
v cs
CS
R 1
Mode control loops: an outer feedback loop that senses
output voltage (current) and delivers a DC control
voltage to an inner feedback loop, which senses the
Switch Off
0.5V
R S
peak current of the inductor and keeps it constant on a
pulse-by-pulse basis. One of the advantages of the
Figure 28.
Cycle-by-Cycle OCP Circuit
Current-Mode control is line/load regulation, which is
corrected instantaneously against line voltage changes
without the delay of an error amplifier.
Programmable Slope Compensation
When the power converter operates in Continuous
Conduction Mode (CCM), the current programmed
controller is inherently unstable when duty is larger than
50%, regardless of the converter topology. The
FAN7340 uses a Peak-Current-Mode control scheme
with programmable slope compensation and includes an
internal transconductance amplifier to accurately control
the output current over all line and load conditions.
An internal R slope resistor (5 k?) connected to sensing
resistor R S and an external resistor R 1 can control the
slope of V SC for the slope compensation. Although the
normal operating mode of the power converter is DCM,
the boost converter operates in CCM in the case of rapid
LED current increas e. As a result, slope compensation
circuit is an important feature.
The value of an external series resistor (R 1 ) can be
programmed by the user. In normal DCM operation, 5 k
Ω is recommended.
? 2013 Fairchild Semiconductor Corporation
FAN7340 ? 1.0.1
12
When the voltage drops at R 1 and R S e xceed a
threshold of approximately 0.5 V, the power MOSFET
over-current function is triggered a fter minimum turn-on
time or LEB time (300 ns).
The peak voltage level at CS terminal:
(4)
Choose the boost switch current-sensing resistor (R CS ):
(5)
Open-LED Protection (OLP)
After the first PWM dimming-HIGH signal, the feedback
sensing resistor (RSENSE) starts sensing the LED
current. If the feedback voltage of the SENSE pin drops
below 0.2 V, the OLP triggers to generate an error flag
signal. Because OLP can be detected only in PWM
dimming-HIGH; if OLP detecting time is over 5 μ s, PWM
dimming signal is pulled HIGH internally regardless of
external dimming signal. If OLP signal continues over
blanking time, an error flag signal is triggered.
OLP blanking time is dependent on boost switch
frequency per Equation (6). FAULT OUT signal is made
through the FO pin, which needs to be connected 5 V
reference voltage through a pull-up resistor. In normal
operation, FO pin voltage is pulled down to ground. In
OLP condition, FO pin voltage is pulled HIGH.
(6)
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